Intel’s 28-core Xeon Skylake CPUs to Support 6TB of DRAM


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    The “Purley” platform will support dual-socket (2S), quad-socket (4S) as well as octa-socket (8S) machines and will rely on Intel’s next-generation a point-to-point processor interconnect UPI (Ultra Path Interconnect) bus, which will replace the company’s current-gen QuickPath Interconnect (QPI) technology.

    The “Purley” server platform will be the first to support six-channel memory per socket, which will provide massive amount of bandwidth to each processor. Besides, the new platform will also be the first to support Intel’s OmniPath 100Gb/s fabric to connect for external compute and I/O nodes, which will greatly increase performance in supercomputer applications.

    Intel will release three different versions of Xeon processors for its “Purley” platform targeting different applications – “Skylake-EP”, “Skylake-EX” and “Skylake-F” – according to a report from CPU World. The new chips will feature up to 28 cores based on the “Skylake” micro-architecture with AVX512 instructions and Hyper-Transport technology, up to six DDR4 memory channels (up to two 2400MHz DIMMs per channel are supported, i.e., up to 768GB of DDR4 memory per socket without SMB), up to 48 PCI Express 3.0 lanes as well as two or three UPI channels per socket.

    • Intel Xeon “Skylake-EP” processors will be aimed at mainstream dual-socket (2S) servers and will thus only have two UPI links. Thermal design power of low-power versions of such processors will range from 45W to 80W, whereas standard high-performance offerings will have TDP of up to 145W. Workstation-class offerings with increased clock-rates will be rated to dissipate up to 160W.

    • Intel Xeon “Skylake-EX” processors will be designed for high-performance and mission critical machines with two, four or even eight sockets, which means that they will feature up to three UPI links. The processors will introduce new RAS [reliability, availability, serviceability] features such as Instruction Retry (pipeline error protection for integers), Advanced Error Detection and Correction as well as Adaptive Dual Device Data Correction, to make next-gen high-end servers even more robust. According to previously released unofficial information, Intel’s forthcoming expandable processors will support four times higher memory capacity (compared to today’s chips) thanks to “Apache Pass” scalable memory buffer (SMB), which means up to 6144GB (over 6TB) per socket, or up to 24576GB of DDR4 RAM per 4S machine. The “Skylake-EX” chips will have TDP of up to 165W.

    • Intel Xeon “Skylake-F” will be aimed at high-performance computing applications (which use 2S platforms) and will incorporate one link of the first-generation OmniPath fabric with 100Gb/s bandwidth. The latter will be supported by the code-named “Storm Lake” chip, which will be incorporated into the Xeon’s multi-chip-module (MCM) package. Among other things, Omni-Path Fabric will be used to connect to next-gen Xeon Phi co-processors.

    The upcoming Xeon “Skylake” processors will use the new socket P0 and will feature flip-chip land-grid array packaging (FC-LGA) with up to 3467 contacts. The final amount of pins to be used is unclear today, but according to unofficial information, it will exceed 3000 balls.

    The dimensions of the new Xeon processor packages will also be considerably larger compared to today’s LGA2011-3. Intel is currently considering 76mm*51mm or 76mm*56mm sizes, CPU World claims. By contrast, today’s Core i7 Extreme and Xeon E5/E7 chips in LGA2011-3 form-factor feature 58.5mm*51mm component size. Mainstream Intel LGA1150 processor come in 37.5mm*37.5mm packages.

    Intel’s 28-core Xeon ‘Skylake’ CPUs to support 6TB of DRAM, LGA-3467 form-factor

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